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DS060

Features: First ASIC replacement FPGA for high-volume production with on-chip RAMDensity up to 1862 logic cells or 40,000 system gatesStreamlined feature set based on XC4000 architectureSystem performance beyond 80 MHzBroad set of AllianceCORE™ and LogiCORE™ predefined solutions availa...

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SeekIC No. : 004328346 Detail

DS060: Features: First ASIC replacement FPGA for high-volume production with on-chip RAMDensity up to 1862 logic cells or 40,000 system gatesStreamlined feature set based on XC4000 architectureSystem perfo...

DS060 Data Sheet

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Part Number:
DS060
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

First ASIC replacement FPGA for high-volume production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE™ and LogiCORE™ predefined solutions available
Unlimited reprogrammability
Low cost



Pinout

Connection Diagram


Specifications

Symbol Description Value Unit
VCC Supply voltage relative to GND 0.5 to +7.0 V
VIN Input voltage relative to GND(2,3) 0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output(2,3) 0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) 65 to +150 °C
TJ Junction temperature Plastic packages +125 °C



Description

All internal routing channels of the DS060 are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing channels is provided to achieve efficient automated routing.

This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block diagram of the CLB routing channels. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design. The following description of the routing channels of the DS060 is for information only and is simplified with some minor details omitted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool.




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