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DS06-10801-4E

Features: • High-speed, large scale ASIC produced in short development time: TAT = One third compared with Standard Cell ASICs (target value)• Uses an architecture that simplifies physical design tasks.• Pre-designed common masters with IR-drop free.• Pre-designed test circ...

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DS06-10801-4E: Features: • High-speed, large scale ASIC produced in short development time: TAT = One third compared with Standard Cell ASICs (target value)• Uses an architecture that simplifies physic...

DS06-10801-4E Data Sheet

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Part Number:
DS06-10801-4E
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• High-speed, large scale ASIC produced in short development time: TAT = One third compared with Standard Cell ASICs (target value)
• Uses an architecture that simplifies physical design tasks.
• Pre-designed common masters with IR-drop free.
• Pre-designed test circuit insertion to reduce test synthesis tasks.
• Uses a dedicated timing-driven layout tool to reduce development time.
• Signal Integrity Free (pre-designed main clock trees without design verifications)
• Max built-in gate number : 6,000,000 gates or more
• Technology : 0.11 m Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
• Internal cells support high-speed operation
• Power supply voltage : +1.2 V ± 0.1 V/2.5 V ± 0.2 V (Dual power supply. Needs 1.5 V power supply during using
HTSL.) .
• Operation junction temperature : −40 to +125 (standard)
• Max operating frequency: 333 MHz (internal circuit)
• Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
• Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
• Embedded macro : PLL, SRAM
• 8-channel clock supply system incorporating a PLL
• Supports Memory-BIST/Boundary-SCAN
• Package : FC-BGA (729 pins to 1681 pins)
• ARM core is supported.


Specifications

Parameter Symbol Application Rating Unit
Min Max
Power supply
voltage		 VDD VDDI (Core) − 0.5 1.8 V
VDDE
(for 2.5 V CMOS I/Os, 3.3 V Tolerant I/Os)		 − 0.5 3.6 V
VDDE (for 1.5 V I/Os*4) − 0.5 3.6 V
Input voltage *1 VI 2.5 V CMOS − 0.5 VDDE + 0.5
( 3.6)		 V
3.3 V Tolerant − 0.5 VDDE + 0.5
( 3.6)		 V
Output voltage VO 3.3 V Tolerant (H/L-State) − 0.5 VDDE + 0.5
( 4.0)		 V
3.3 V Tolerant (Z-State) − 55 4.0 V
Storage
temperature		 Tst − 55 + 125
Operation
junction
temperature		 Tj − 40 + 125
Power supply
pin current *2		 ID Each VDDE pin 180 mA
Each VDDI pin 200 mA
Each VSS pin 200 mA
Output current *3 IO 2.5 V CMOS ±10 mA
3.3 V Tolerant ±7.5 mA
           

*1 : Different limit values apply for LVDS, etc.
*2 : Maximum supply current in normal operation. Supply current depends on the frame or the package.
*3 : Maximum output current in normal operation
*4 : Required when using HSTL I/O.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.


Description

DS06-10801-4E is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.

By using 0.11 m CMOS process technology, the DS06-10801-4Es can support 6 million logic gates, 4.55 Mbits SRAM and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins) packages are available.

* :DS06-10801-4E is a trademark of Fujitsu Limited.




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