DP849001

Features: Operates at Non-Return to Zero (NRZ) data rates up to 25 Mbits/secondSingle a5V power supply operationLow Power dissipationÐ110 mW at 25 Mbits/sec NRZ rateTTL compatible inputs and outputsSupports write data precompensation with Early, Late and Level (PCOMP3T) output signalsPower Dow...

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DP849001 Picture
SeekIC No. : 004328017 Detail

DP849001: Features: Operates at Non-Return to Zero (NRZ) data rates up to 25 Mbits/secondSingle a5V power supply operationLow Power dissipationÐ110 mW at 25 Mbits/sec NRZ rateTTL compatible inputs and out...

floor Price/Ceiling Price

Part Number:
DP849001
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

 Operates at Non-Return to Zero (NRZ) data rates up to 25 Mbits/second
 Single a5V power supply operation
 Low Power dissipationÐ110 mW at 25 Mbits/sec NRZ rate
 TTL compatible inputs and outputs
 Supports write data precompensation with Early, Late and Level (PCOMP3T) output signals
 Power Down Mode included
 DC-erasure is available to support analog flaw map testing
 Bypass mode available which permits un-encoded test
   patterns to be issued at the CODEOUT pin



Pinout

  Connection Diagram


Specifications

Supply Voltage ..............................................................7V
TTL Input Maximum Voltage ..........................................7V
Maximum Output Voltage.............................................. 7V
ESD Susceptibility ......................................2000V (Note 1)



Description

The DP84900 is designed to perform the encoding and decoding for disk memory systems. DP849001 is designed to interface directly with National Semiconductor's integrated read channel circuits such as the DP8492. This Encoder/ Decoder (ENDEC) circuit decoding employs a 2/3 (1,7) Run Length Limited (RLL) code type and supports hard sectored format. The decoding also includes write data precompensation circuitry which detects the need for precompensation. This circuitry issues early, late and level (PCOMP3T) output signals necessary for two levels of precompensation. Precompensation information is generated against both the 2T and 3T patterns. The precompensation circuitry can be bypassed by the setting of a bit in the control register.

A control register is included to configure the ENDEC and to select several device operation options such as output code inversion and TRI-STATEÉ of the NRZ output.

The DP84900 is available in a 20-pin SO and SSO package.




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