Features: · Detects and corrects single-bit errors
· Detects and flags double-bit errors
· Built-in diagnostic capability
· Fast write and read cycle processing times
· Byte-write capability . . . DP8402A and DP8403
· Fully pin and function compatible with TI's SN74ALS632A thru SN74ALS635 seriesPinoutSpecificationsSupply Voltage, VCC (See Note 1) 7V
Input Voltage: CB and DB 5.5V
All Others 7V
Operating Free-Air Temperature: Military -55 to +125
Commercial ° to +70
Storage Temperature Range -65 to +150DescriptionThe DP8402A, DP8403, DP8404 and DP8405 devices are 32-bit parallel error detection and correction circuits (EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404 and DP8405 600-mil packages. The EDACs use a modified Hamming code to generate a 7-bit check word from a 32-bit data word. This check word is stored along with the data word during the memory write cycle. During the memory read cycle, the 39-bit words from memory are processed by the EDACs to determine if errors have occurred in memory.
Single-bit errors in the 32-bit data word are flagged and corrected. Single-bit errors in the 7-bit check word are flagged, and the CPU sends the EDAC through the correction cycle even though the 32-bit data word is not in error. The correction cycle will simply pass along the original 32-bit data word in DP8403 and produce error syndrome bits to pinpoint the error-generating location.
Double bit errors are flagged but not corrected. These errors may occur in any two bits of the 39-bit word from memory (two errors in the 32-bit data word, two errors in the 7-bit check word, or one error in each word). The gross-error condition of all lows or all highs from memory will be detected. Otherwise, errors in three or more bits of the 39-bit word are beyond the capabilities of these devices to detect. Read-modify-write (byte-control) operations can be performed with the DP8402A and DP8403 EDACs by using output latch enable, LEDBO, and the individual OEB0 thru OEB3 byte control pins.
Diagnostics are performed on the EDACs by controls and internal paths that allow the user to read the contents of the DB and CB input latches. These will determine if the failure occurred in memory or in the EDAC.