DP8430V

Features:

On chip high precision delay line to guarantee critical DRAM access timing parameters microCMOS process for low power
High capacitance drivers for RAS CASWE and DRAM address on chip
On chip support for nibble page and static column DRAMs
Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic
Can use a single clock source Up to 33 MHz operating frequency
On board Port APort B (DP8432V only)refresh arbitration logic
Direct interface to all major microprocessors
4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable)


Pinout




Specifications

TemperatureunderBias......................................................0to +70
StorageTemperature ...................................................-65to +150
All Input or Output Voltage
    withRespecttoGND....................................................... -0.5Vto+ 7V
PowerDissipation 20MHz.............................................................0.5W
ESDRating..................................................................................2000V
TemperatureCycle ..........................................................300of0/125


Description

The DP8430V31V32V dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8430V31V32V generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge An additional feature of the DP8432V is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip