DP8420AV-20

Features:


 On chip high precision delay line to guarantee critical DRAM access timing parameters
 microCMOS process for low power
 High capacitance drivers for RAS, CAS, WE and DRAM address on chip
 On chip support for nibble, page and static column DRAMs
 Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic
 Selection of controller speeds: 20 MHz and 25 MHz
 On board Port A/Port B (DP8422A only)/refresh arbitration logic
 Direct interface to all major microprocessors (application notes available)
 4 RAS and 4 CAS drivers (the RAS and CAS configuration is programmable)


Pinout




Specifications

Temperature under Bias ------------0ßC to a70ßC
Storage Temperature ---------------b65ßC to a150ßC

All Input or Output Voltage
with Respect to GND-----------------b0.5V to a7V
Power Dissipation @ 20 MHz---------------0.5W
ESD Rating to be determined.

Description

The DP8420A/21A/22A dynamic RAM controllers provide a low cost, single chip interface between dynamic RAM and all 8-, 16- and 32-bit systems. The DP8420A/21A/22A generate all the required access control signal timing for DRAMs. An on-chip refresh request clock is used to automatically refresh the DRAM array. Refreshes and accesses are arbitrated on chip. If necessary, a WAIT or DTACK output inserts wait states into system access cycles, including burst mode accesses. RAS low time during refreshes and RAS precharge time after refreshes and back to back accesses are guaranteed through the insertion of wait states. Separate on-chip precharge counters for each RAS output can be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional feature of the DP8422A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on chip.