DP8228M

Features:

Single chip system controller and bus driver for 8080A Microcomputer Systems
Allows use of multibyte CALL instructions for Interrupt Acknowledge
Provides user-selected single-level interrupt vector (RST 7)
Provides isolation of data bus
Supports a wide variety of system bus structures
Reduces system component count
DP8238DP8238M provides advanced InputOutput Write and Memory Write control signals for large system timing control


Specifications

StorageTemperature ...........................................-65to+ 150
SupplyVoltage....................................................V_CC- 0.5to +7V
InputVoltage ..........................................................-1.5Vto +7V
OutputCurrent ...............................................................100mA
Maximum Power Dissipation at 25
   CavityPackage .........................................................2179mW
   MoldedPackage ........................................................2361mW


Description

The DP8228DP8228M DP8238DP8238M are system controllerbus drivers contained in a standard 28-pin dual- in-line package The chip DP8228M which is fabricated using Schottky Bipolar technology generates all the read and write control signals required to directly interface the memory and input
output components of the 8080A microcomputer family The chip DP8228M also provides drive and isolation for the bidirectional data bus of the 8080A microprocessor Data bus isolation enables the use of slower memory and inputoutput components in a system and provides for enhanced system noise immunity

A user-selected signal-level interrupt vector (RST 7) is provided by DP8228M for use in the interrupt structure of small systems that need only one basic vector No additional components (such as an interrupt instruction port) are required to use the single interrupt vector in these systems DP8228M also generate an Interrupt Acknowledge (INTA) control signal for each byte of a multibyte CALL instruction when an interrupt is acknowledged by the 8080A This feature permits the use of a multilevel priority interrupt structure in large interrupt-driven systems