CY7B993V

The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver of CY7B993V and CY7B994V provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.

CY7B993V and CY7B994V feature a guaranteed maximum TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process.

Eighteen configurable outputs of CY7B993V and CY7B994V each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 1 to 4 of four outputs allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 6251300-ps increments up to 10.4 ns. One of the output banks, CY7B993V and CY7B994V includes an independent clock invert function. The feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs.

Selectable reference input of CY7B993V and CY7B994V is a fault tolerance feature that allows smooth change-over to secondary clock source, when  the primary clock source is not in operation. The reference inputs and feedback inputs of CY7B993V and CY7B994V are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout.