CY7B9911V

Features: • All output pair skew <100 ps typical (250 max.)• 3.75- to 110-MHz output operation• User-selectable output functions- Selectable skew to 18 ns- Inverted and non-inverted- Operation at 1⁄2 and 1⁄4 input frequency- Operation at 2x and 4x input frequency (...

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SeekIC No. : 004319569 Detail

CY7B9911V: Features: • All output pair skew <100 ps typical (250 max.)• 3.75- to 110-MHz output operation• User-selectable output functions- Selectable skew to 18 ns- Inverted and non-inve...

floor Price/Ceiling Price

Part Number:
CY7B9911V
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• All output pair skew <100 ps typical (250 max.)
• 3.75- to 110-MHz output operation
• User-selectable output functions
- Selectable skew to 18 ns
- Inverted and non-inverted
- Operation at 1⁄2 and 1⁄4 input frequency
- Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50 terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter 100 ps (typical)



Pinout

  Connection Diagram


Specifications

(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage to Ground Potential .................. 0.5V to +7.0V
DC Input Voltage.............................................  0.5V to +7.0V
Output Current into Outputs (LOW)................................. 64 mA
Static Discharge Voltage...............................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current....................................................... > 200 mA



Description

The CY7B9911V 3.3V RoboClock+™ High-Speed Low- Voltage Programmable Skew Clock Buffer (LVPSCB) offers user-selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, CY7B9911V can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews and full-swing logic levels (LVTTL).

Each output of CY7B9911V can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal "zero" skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this "zero delay" capability of the LVPSCB CY7B9911V is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions of CY7B9911V are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock, CY7B9911V can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.




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