CY3148

Features: • Seamless integration with your Cadence Concept™ and simulation tools• Supports pre-synthesis simulation using Leapfrog™• Powerful schematic symbol library• IEEE-compliant VHDL• Supports the full UltraLogic™ family of SPLDs and CPLDs•...

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CY3148: Features: • Seamless integration with your Cadence Concept™ and simulation tools• Supports pre-synthesis simulation using Leapfrog™• Powerful schematic symbol library&#...

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Part Number:
CY3148
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Seamless integration with your Cadence Concept™ and simulation tools
• Supports pre-synthesis simulation using Leapfrog™
• Powerful schematic symbol library
• IEEE-compliant VHDL
• Supports the full UltraLogic™ family of SPLDs and CPLDs
• Industry-leading synthesis for programmable logic
• 100% automatic fitting
• VHDL and Verilog post-layout timing models
• Complete solution from design entry to programming



Description

CY3148 Design Entry and Pre-Synthesis Simulation Design with ease using schematic symbols, VHDL, or a combination of both, supported with Cadence's Concept tool available with your Cadence flow. Prior to synthesis, you can use Leapfrog™ to verify your functionality.

Synthesis Your entire design is automatically converted into VHDL and efficiently synthesized into a SPLD or CPLD device using Warp. UltraGen™ synthesis technology will ensure that you achieve the best results for every Cypress device. For a description of UltraGen and synthesis, see the Warp datasheets.

Fitting Easily retarget your design to different devices. The 100% automatic fitting tools produce optimal results in minutes.

Post-Synthesis Simulation Warp outputs VHDL and Verilog timing simulation models. Verify your design with timing using your choice of Cadence's Leapfrog™ VHDL or Verilog-XL™ simulators or any other VHDL or Verilog simulator.

Programming Warp generates JEDEC programming files for all Cypress devices which can be used for in-system reprogramming (ISR™) or with various device programmers.

System Requirements For Sun Workstations SPARC CPU SunOS 4.1.3 or Solaris 2.5 CD-ROM drive Ordering Information CY3148 Cypress Cadence Bolt-in Kit includes: CD-ROM with Bolt-in software and on-line documentation CD-ROM with Warp software and on-line documentation Warp User's Guide and Reference Manual Release Notes VHDL for Programmable Logic Textbook Document #: 38-00681-B SunOS and Solaris are trademarks of Sun Microsystems Corporation.

Concept, Leapfrog, and Verilog-XL are trademarks of Cadence Design System, Inc.

ISR, UltraGen, UltraLogic, and Warp are trademarks of Cypress Semiconductor Corporation.


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