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CY28352

Features: • 60- 200-MHz operating frequency• Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications• Distributes one clock input to six differential outputs• External feedback pin FBIN is used to synchronize output to clock input̶...

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SeekIC No. : 004319234 Detail

CY28352: Features: • 60- 200-MHz operating frequency• Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications• Distributes one clock input to six diff...

CY28352 Data Sheet

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Part Number:
CY28352
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/8/14

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Product Details

Description



Features:

• 60- 200-MHz operating frequency
• Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize output to clock input
• Conforms to DDRI specification
• Spread Aware™ for electromagnetic interference (EMI) reduction
• 28-pin SSOP package


Pinout

Connection Diagram


Specifications

Input Voltage Relative to VSS:.............................. VSS 0.3V
Input Voltage Relative to VDDQ or AVDD:............ VDD + 0.3V
Storage Temperature: ................................65°C to + 150°C
Operating Temperature: ....................................0°C to +70°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).


Description

This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels.

CY28352 is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN.

The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

The PLL in CY28352 uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, lowjitter output differential clocks.




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