CY28351

• Supports 333-MHz and 400-MHz DDR SDRAM
• 60- 200-MHz operating frequency
• Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications
• Distributes one clock input to ten differential outputs
• External feedback pin (FBIN) is used to synchronize the outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI) reduction
• 48-pin SSOP package

Input Voltage Relative to V_SS:.............................. V_SS 0.3V
Input Voltage Relative to V_DDQ or AV_DD: ............. V_DD + 0.3V
Storage Temperature: ................................65°C to +150°C
Operating Temperature: ...................................0°C to +70°C
Maximum Power Supply: .................................................3.5V

This PLL clock buffer is designed for 2.5-V_DD and 2.5-AVDD operation and differential outputs levels.

This CY28351 is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.

The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AV_DD is grounded, the PLL is turned off and bypassed for the test purposes.

The PLL in CY28351 uses the input clock (CLKIN) and the feedback clock (FBIN) to provide high-performance, low-skew, low-jitter output differential clocks.