CX74061

Features: · Two-step gain control PCS LNA· Three-step gain control cellular LNA· GPS LNA· External resistor to adjust LNA bias current· Independent AMPS, CDMA, PCS, and GPS mixers· Single LO input for CDMA and PCS mixer· Buffered LO signal for transmit upconverter· Single external UHF VCO for PLL ...

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SeekIC No. : 004317991 Detail

CX74061: Features: · Two-step gain control PCS LNA· Three-step gain control cellular LNA· GPS LNA· External resistor to adjust LNA bias current· Independent AMPS, CDMA, PCS, and GPS mixers· Single LO input f...

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Part Number:
CX74061
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/7/15

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Product Details

Description



Features:

· Two-step gain control PCS LNA
· Three-step gain control cellular LNA
· GPS LNA
· External resistor to adjust LNA bias current
· Independent AMPS, CDMA, PCS, and GPS mixers
· Single LO input for CDMA and PCS mixer
· Buffered LO signal for transmit upconverter
· Single external UHF VCO for PLL circuitry
· 90 dB dynamic range VGA
· 200 to 600 MHz VHF oscillator
· VCO_ON control for current optimization
· Battery cell operation (2.7 V < Vcc < 3.3 V)
· 7 x 7 mm 48-pin RFLGA™ package with down-set paddle



Application

· Tri-band, quad-mode handsets
· PCS and GPS phones
· CDMA and GPS phones



Description

The CX74061 Application-Specific Integrated Circuit (ASIC) is a single Intermediate Frequency (IF), multi-mode, tri-band receiver intended for use in Code Division Multiple Access (CDMA) phones in Personal Communications System (PCS), cellular CDMA, Advanced Mobile Phone System (AMPS), and Global Positioning System (GPS) modes.
The CX74061 is a highly integrated super-heterodyne receiver. Except for the Surface Acoustic Wave (SAW) filters and matching components, CX74061 incorporates all the components required to implement the receiver chain, from the Low-Noise Amplifier (LNA) to the In-Phase and Quadrature (I/Q) demodulator stages. Three LNAs are in the front-end receiver: a three-step gain stage cellular LNA (high, mid, and bypass), a two-step gain stage PCS LNA (high, bypass), and a high gain stage GPS LNA.

After RF LNA signal amplification and filtering from the antenna, the received signal is mixed down from RF to the IF. There are separate mixers for AMPS, CDMA-cellular, CDMAPCS, and GPS modes. The CDMA and PCS mixers have balanced outputs for the IF SAW filters, while the AMPS differential output can be combined externally to mate to a single-ended SAW filter. The GPS mixers have a differential output for an external L-C bandpass filter. After IF filtering, the IF signal is amplified by a Variable Gain Amplifier (VGA) and fed to an I/Q demodulator, resulting in baseband I/Q signals at the output.

The CX74061 is also designed with two Local Oscillator (LO) input ports, one for the AMPS/CDMA/PCS mixer and one for the GPS mixer. These mixers operate at different RF frequency inputs, but have the same IF frequency output. This usually refers to a single IF (SIF) plan at 183.6 MHz.

CX74061 PCS/CELL_LO signal (pin 36) provides an LO port for the CDMA-cellular and CDMA-PCS mixers. The PCS band is selected by default as an input LO frequency to the PCS mixer. In the cellular band, the frequency is divided by two by an internal divider, which provides the LO input to the cellular mixer. Only one external VCO is required for the UHF PLL. Additionally, the mixer LO signal is coupled and amplified internally, which provides another RF signal to drive the transmtiter upconverter LO port.

The VGA has a minimum dynamic range of 90 dB with a control voltage range of 0.3 to 2.5 V, which is common to all modes. A VHF oscillator operates with external tank circuits to provide LO frequencies for the I/Q demodulator in the cellular, PCS, and GPS modes.

The noise figure, gain, and third order Input Intercept Point (IIP3) of each stage in the receiver chip are optimized to meet the system requirements for AMPS and CDMA modes according to TIA/EIA-98-C. The ASIC design employs BiCMOS technology for low cost, high performance, and a high level of integration.

A block diagram of the CX74061 is shown in Figure 1.




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