CGS702V

Features:

`Reduced EMI compared to CGS700 (refer to EMI characteristics)
`Guaranteed and tested: 500 ps pin-to-pin skew (T_OSHL and T_OSLH) on 1x outputs
`PentiumTM and PowerPCTM compatible
`Output buffer of nine drivers for large fanout
`25 MHz±160 MHz output frequency range
`Outputs operating at 4x, 2x, 1x of the reference frequency for multi-frequency bus applications
`Selectable output frequency
`Internal loop filter to reduce noise and jitter
`Separate Analog and digital VCC and Ground pins
`Low frequency test mode by disabling the PLL
`Implemented on National's Core CMOS process
`Symmetric output current drive: +30 mA/b30 mA I_OL/I_OH
`28-pin PCC for optimum skew performance
`Guaranteed 2 kV ESD protection


Pinout




Specifications

Supply Voltage (V_CC)                                    -0.5V to 7.0V
DC Input Voltage Diode Current (I_IK)
V = -0.5V -20 mA
V = VCC+ 0.5V                                                     +20 mA
DC Input Voltage (V_I)                           -0.5V to VCC +0.5V
DC Output Diode Current (I_O)
V = -0.5V                                                                 -20 mA
V = V_CC + 0.5V                                                       +20 mA
DC Output Voltage (V_O)                       -0.5V to VCC +0.5V
DC Output Source
or Sink Current (I_O)                                                ±60 mA
DC VCC or Ground Current
per Output Pin (I_CO or I_GND)                                 ±60 mA
Storage Temperature (T_STG)                       -65 to +150
Junction Temperature                                                  150
Power Dissipation (Static and Dynamic) (Note 2)   1400 mW


Description

The CGS702 is an off-the-shelf clock driver specifically designed for today's high speed processors. It provides low skew outputs which are produced at different frequencies from three fixed input references. The CGS702 is a reduced EMI version of the CGS700. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz, 33 MHz or 40 MHz.

The CGS702V PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input.

CGS702V includes a TRI-STATE® control pin to disable the outputs while the PLL is still in lock. This function allows testing the board without having to wait to acquire the lock once the testing is complete. (Continued)