CGS701AV

Features:

`Guaranteed: 400 ps pin-to-pin skew (tOSHL and tOSLH) on 1X outputs.
`Pentium ®and PowerPCTM compatible
`g300 ps propagation delay
`Output buffer of eight drivers for large fanout
`25 MHz±160 MHz output frequency range
`Outputs operating at 4X, 2X, 1X of the reference frequency for multifrequency bus applications
`Selectable output frequency
`Internal loop filter to reduce noise and jitter
`Separate analog and digital VCC and ground pins
`Low frequency test mode by disabling the PLL
`Implemented on National's Core CMOS process
`Symmetric output current drive: a30/b30 mA IOL/IOH
`Industrial temperature of b40ßC to a85ßC
`28-pin PLCC for optimum skew performance
`Guaranteed 2k volts ESD protection


Specifications

Supply Voltage (V_CC)                                       -0.5V to +7.0V
DC Input Voltage Diode Current (I_IK)
V = -0.5V                                                                      -20 mA
V = V_CC + 0.5V +20 mA
DC Input Voltage (V_I)                              -0.5V to VCC + 0.5V
DC Output Diode Current (I_O)
V = -0.5V                                                                     -20 mA
V = V_CC + 0.5V                                                           +20 mA
DC Output Voltage (VO)                           -0.5V to VCC + 0.5V
DC Output Source
or Sink Current (I_O)                                                   ±60 mA
DC VCC or Ground Current
per Output Pin (I_CC or I_GND)                                     ±60 mA
Storage Temperature (T_STG)                          -65 to +150
Junction Temperature                                                     150
Power Dissipation
(Static and Dynamic) (Note B)                                   1400 mW

Description

CGS701A is an off the shelf clock driver specifically designed for today's high speed designs. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from a 25 MHz±40 MHz crystal oscillator.

The CGS701AV PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input.

CGS701AV includes a TRI-STATE® control pin to disable the outputs. This feature allows for low frequency functional testing and debugging.

Also included, is an EXTSEL pin to allow testing the chip via an external source. The EXTSEL pin, once set to high, causes the External-ClockMUX to change CGS701AV's input from the output of the VCO and Counter to the external clock signal provided via SKWTST input pin. (continued)