PinoutDescriptionThe CDCLVD2106 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. Features of the CDCLVD2106 are:(1)Dual 1:6 Differential Buffe...
CDCLVD2106: PinoutDescriptionThe CDCLVD2106 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be appl...
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The CDCLVD2106 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Features of the CDCLVD2106 are:(1)Dual 1:6 Differential Buffer; (2)Low Additive Jitter: <300 fs rms in 10 kHz 20 MHz; (3)Low Within Bank Output Skew of 45 ps (Max); (4)Universal Inputs Accept LVDS, LVPECL,LVCMOS; (5)One Input Dedicated for Six Outputs; (6)Total of 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible; (7)Clock Frequency up to 800 MHz; (8)2.3752.625 V Device Power Supply; (9)LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs; (10)Industrial Temperature Range 40°C to 85°C; (11)Packaged in 6 mm x 6 mm 40-pin QFN (RHA); (12)ESD Protection Exceeds 3-kV HBM, 1-kV CDM.
The absolute maximum ratings of the CDCLVD2106 can be summarized as:(1)Supply voltage range :0.3 to 2.8 V; (2)Input voltage range :0.2 to (VCC + 0.2) V; (3)Output voltage range: 0.2 to (VCC + 0.2) V; (4)Electrostatic discharge (HBM, 1.5 k, 100 pF): >3000 V.
If you want to know more CDCLVD2106 information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .