CDCLVD2102

The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

Features of the CDCLVD2102 are:(1)Dual 1:2 Differential Buffer; (2)Low Additive Jitter <300 fs RMS in 10-kHz to 20-MHz; (3)Low Within Bank Output Skew of 15 ps (Max); (4)Universal Inputs Accept LVDS, LVPECL,LVCMOS; (5)One Input Dedicated for Two Outputs; (6)Total of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible; (7)Clock Frequency up to 800 MHz; (8)2.3752.625V Device Power Supply; (9)LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs; (10)Industrial Temperature Range 40°C to 85°C; (11)Packaged in 3mm * 3mm 16-Pin QFN (RGT); (12)ESD Protection Exceeds 3 kV HBM, 1 kV CDM.

The absolute maximum ratings of the CDCLVD2102 can be summarized as:(1)Supply voltage range, VCC :0.3 to 2.8 V; (2)Input voltage, VI :0.2 to (VCC + 0.2) V; (3)Output voltage range, VO: 0.2 to (VCC + 0.2) V; (4)Driver short circuit current, IOSD :See Note (2); (5)Electrostatic discharge (HBM, 1.5 k, 100 pF) :>3000 V.

If you want to know more CDCLVD2102 information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .