CDCLVD1213

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

Features of the CDCLVD1213 are:(1)1:4 Differential Buffer; (2)Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz; (3)Low Output Skew of 20 ps (Max); (4)Selectable Divider Ratio 1, /2, /4; (5)Universal Input Accepts LVDS, LVPECL, and CML; (6)4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible; (7)Clock Frequency up to 800 MHz; (8)2.375 V2.625 V Device Power Supply; (9)Industrial Temperature Range: 40°C to 85°C; (10)Packaged in 3 mm * 3 mm 16-Pin QFN (RGT); (11)ESD Protection Exceeds 3 kV HBM, 1 kV CDM.

The absolute maximum ratings of the CDCLVD1213 can be summarized as:(1)Supply voltage range, VCC: 0.3 to 2.8 V; (2)Input voltage range, VI: 0.2 to (VCC + 0.2) V; (3)Output voltage range, VO :0.2 to (VCC + 0.2) V; (4)Driver short circuit current, IOSD :See Note (2); (5)Electrostatic discharge (Human Body Model, 1.5 k, 100 pF):>3000 V.

If you want to know more CDCLVD1213 information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .