CDC330

Features: • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications• TTL-Compatible Inputs and Outputs• Two Banks Distribute One Clock Input to Three Same-Frequency Clock Outputs• One Bank Distributes One Clock Input to Four Half-Frequency C...

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CDC330 Picture
SeekIC No. : 004312261 Detail

CDC330: Features: • Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications• TTL-Compatible Inputs and Outputs• Two Banks Distribute One Clock Input to Thr...

floor Price/Ceiling Price

Part Number:
CDC330
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
• TTL-Compatible Inputs and Outputs
• Two Banks Distribute One Clock Input to Three Same-Frequency Clock Outputs
• One Bank Distributes One Clock Input to Four Half-Frequency Clock Outputs
• Internal Power-Up Circuit
• Distributed VCC and Ground Pins Reduce Switching Noise
• Symmetrical Output Drive (32-mA IOH, 32-mA IOL)
• State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• Packaged in Plastic Small-Outline Package



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .  .0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . .  .0.5 V to 5.5 V
Current into any output in the low state, IO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .96 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .18 mA
Output clamp current, IOK (VO < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2)  . . . . . . . . . . . . . . .  . . . . . . . . .1.6 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C



Description

The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring output signals at both the primary clock frequency and one-half the primary clock frequency.

CDC330 contains two banks that fan out one input to three same-frequency outputs and one bank that fans out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the frequency of their clock (2A) input.

When CDC330 output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to the high level. When a bank's OE input is high, the outputs are in the high-impedance state.

The CDC330 is characterized for operation from 0°C to 70°C.




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