BS616LV2019TI-55

The BS616LV2019TI-55 is designed as one kind of high performance , very low power CMOS Static Random Access Memory that has an automatic power down feature, reducing the power consumption significantly when chip is deselected and is available in DICE form , JEDEC standard 48-pin TSOP Type I package and 48-ball BGA package.

Features of the BS616LV2019TI-55 are:(1)Data retention supply voltage as low as 1.5 V;(2)Fully static operation;(3)Three state outputs and TTL compatible; (4)Automatic power down when chip is deselected;(5);(6)High speed access time: 55 or 70 ns;(7)Vcc operation voltage range: 2.7V to 3.6V.

The absolute maximum ratings of the BS616LV2019TI-55 can be summarized as:(1)Terminal Voltage with Respect to GND: -0.5 V to Vcc+0.5 V;(2)Power Supply: -0.5 V to Vcc+0.5 V;(3)Temperature Under Bias: -40 to +85 ;(4)Storage Temperature: -60 to +150 ;(5)Power Dissipation: 1.0 W;(6)DC Output Current: 20 mA. If you want to know more information about it, please download the datasheet in www.seekic.com or www.chinaicmart.com .