Features: · Power Monitoring and Switching for Non-Volatile Control of SRAMs· Input Decoder Allows Control of 1 or 2 Banks of SRAM· Write-Protect Control· 3-V Primary Cell Input· 3.3-V Operation· Reset Output for System Power-On Reset· Less than 20-ns Chip Enable Propagation Delay· Small 16-Lead T...
BQ2205L: Features: · Power Monitoring and Switching for Non-Volatile Control of SRAMs· Input Decoder Allows Control of 1 or 2 Banks of SRAM· Write-Protect Control· 3-V Primary Cell Input· 3.3-V Operation· Re...
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bq2205LY | UNIT | ||
Input voltage range | VCC, (wrt VSS) | −0.3 to 6.0 | V |
BCP, (wrt VSS) | −0.3 to 4.5 | ||
all other pins, (wrt VSS) | −0.3 to VCC + 0.3 | ||
Operating temperature range, TA | −20 to 70 | ||
Storage temperature, Tstg | −55 to 125 | ||
Temperature under bias, TJbias | −40 to 85 | ||
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds | 300 |
(2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The CMOS bq2205 SRAM non-volatile controller with reset provides all the necessary functions for converting one or two banks of standard CMOS SRAM into non-volatile read/write memory. A precision comparator monitors the 3.3-V VCC input for an out-of-tolerance condition. When out-of-tolerance is detected, the two conditioned chip-enable outputs of BQ2205L are forced inactive to write-protect both banks of SRAM.
Power for the external SRAMs, VOUT, is switched from the VCC supply to the battery-backup supply as VCC decays. On a subsequent power-up, the VOUT supply is automatically switched from the backup supply to the VCC supply. The external SRAMs of BQ2205L are write-protected until a power-valid condition exists. The reset output provides power-fail and power-on resets for the system. During power-valid operation, the input decoder, A, selects one of two banks of SRAM.