BBT3821

The nLiten BBT3821 is a fully integrated octal 2.488Gbps to 3.1875Gbps Clock and Data Recovery (CDR) circuit and Retimer ideal for high bandwidth serial electrical or optical communications systems. It extracts timing information and data from serial inputs at 2.488Gbps to 3.1875Gbps, covering 10 Gigabit Fiber Channel (10GFC) and IEEE 802.3 specified 10 Gigabit Ethernet eXtended Attachment Unit Interface (XAUI) rates.

Each BBT3821 accepts two sets of four high-speed differential serial signals, re-times them with a local Reference Clock, reduces jitter, and delivers eight clean high-speed signals. The BBT3821 provides a full-function XAUI-to-10GBASE-CX4 PMA/PMD (compatible with the IEEE 802.3ak specification), and also can be configured to provide the electrical portion of a XAUI-to-10GBASE-LX4 PMA/PMD, needing only laser drivers and photo detectors to be added. In both these applications, the XAUI side can be configured to implement the XENPAK MSA_R3.0 specification, including full NVR and DOM support. The XPAK and X2 specifications currently all reference the XENPAK specification, and are supported in exactly the same manner. The BBT3821 can also be used to enhance a single full-duplex 10 Gigabit XAUI link, extending the driving distance of the high-speed (2.488Gbps to 3.1875Gbps) differential traces to 40 inches of FR4 PCB (assuming a proper impedance-controlled layout).

Each lane can operate independently with a data transfer rate of within ±100ppm of either 20x or 10x the local Reference Clock. The reference clock should be 156.25MHz for 10 Gigabit Ethernet XAUI applications, and 159.375MHz for 10 Gigabit Fiber Channel. Other reference frequencies can be used for proprietary rates. For other applications, each of the 8 lanes can be operated independently, within the same data rate and clock restrictions.

The nLiten BBT3821 contains eight clock & data recovery units, 8B/10B decoders and encoders, and elastic buffers which provide the user with a simple interface for transferring data serially and recovering it on the receive side. When recovering an 8B/10B stream, a receive FIFO aligns all incoming serial data to the local reference clock domain, adding or removing IDLE sequences as required. This simplifies implementation of an upstream ASIC by removing the requirement to deal with multiple clock domains. The Retimer can also be configured to operate as eight nonencoded 10-bit Retimers. Allowing long strings of consecutive 1's or 0's (up to 512 bits), the nLiten BBT3821 has the capacity to accommodate proprietary encoded data links at any data rate between 2.488Gbps and 3.1875Gbps (and for half rate operation from 1.244Gbps to 1.59375Gbps).

The device configuration can be done through the use of the two line Management Data Input/Output (MDIO) Interface specified in IEEE 802.3 Clause 45. The BBT3821 supports a 5-bit Port Address, and DEVice ADdresses (DEVAD) 1, 3 & 4. The initial values of the registers default to values controlled, where appropriate, by external configuration pins, and set to optimize the initial configuration for XAUI, CX4, and XENPAK/XPAK/X2 use. Optionally, the BBT3821 configuration can be loaded at power-on or reset from the NVR EEPROM or DOM used for the XENPAK/XPAK/X2 registers.

A full suite of loopback configurations is provided, including the (802.3ae required) XAUI-transmit to XAUI-receive loopback, and also the (802.3ae optional) PHY XGXS loopback (effectively CX4/LX4-receive to CX4/LX4 transmit). Lane-by-lane diagnostic loopback is available through vendor-specific MDIO registers.

The low-power version BBT3821LP-JH is selected for operation as an LX4 device at lowered supply voltages.