BBT3420

Features:

• Four channels of transmitter and receiver with serial data transfer rates of 2.488-3.1875Gbps/channel with full rate and half-rate operations
• Up to 12.75Gbps data rate at full duplex
• User-controlled dual-speed operation (per channel) 2.488- 3.1875Gbps or 1.244-1.59Gbps
• IEEE 802.3ae-2002 10 GE and 10 GFC compliant
- XAUI, XGMII, and MDC/MDIO interfaces
• XGMII format 10-bit parallel input/output data
- Supports HSTL 1.8V and 2.5V SSTL_2
• Extensive configuration via 802.3-compliant MDC/MDIO serial interface
• 8bit/10bit Encoding/Decoding per channel with selectable parallel input/output data sizes
- Support optional 8b/10b encoder/decoder bypass operation
• Integrated Equalization and Pre-emphasis
• De-skewing and channel-to-channel alignment options
• Low power, 250mW per channel typical
• Meets jitter requirements with significant margin
• Comma detection and synchronization, byte alignment
• Tx/Rx rate matching via IDLE insertion/deletion
• Receive signal detect and 16 levels of transmission medium equalization
• CML transmit outputs with four levels of pre-emphasis
• Loopback
- Per-channel serial Tx-to-Rx and Rx-to-Tx parallel internal loopback modes
• Single-ended/differential input Reference clock
• Double Data-Rate (DDR) mode, also optional SDR (Single Data Rate) on transmitter
• Support both source-centered and source-simultaneous clocking
• Long Run Length (512 bit) frequency lock ideal for proprietary encoding schemes Transmit byte clock schemes
- One Transmit Byte Clock (TBC) for each channel, or one TBC for all four channels
• Received clock schemes
- Receive data aligned to local reference clock, to recovered clock for each channel, or to recovered clock for Channel A only
• Supports Built-In Self Test (BIST) and IEEE 1149.1 JTAG
• On-chip 25 series output terminations (XGMII side)
• Standard 0.18m 1.8V CMOS technology
• 3.3V tolerant I/O




Specifications

SYMBOL	PARAMETER	UNITS	MIN	MAX
VDDQ	Parallel I/O Power Supply Voltage	V	-0.5	4.6
VDDA, VDD	Other Power Supply Voltages	V	-0.5	2.5
VINCML	CML DC Input Voltage	V	-0.5	VDD + 0.5
VINXSTTL	HSTL/SSTL_2 DC Input Voltage	V	-0.5	5.5
IOUTCML	CML Output Current	mA	-50
IOUXSTTL	HSTL/SSTL_2 Output Current	mA		50
TSTG	Storage Temperature	°C	-65	150
TJ	Junction Temperature	°C	-55	125
TSOL	Soldering Temperature (10s)	°C		220
V ESD	Maximum Input ESD (HBM)	V	-1500	1500

These ratings are those which if exceeded may cause permanent damage to the device. Operation at these or any other conditions in excess of those listed under Operating Conditions below is not implied. Continued exposure to these ratings may reduce device reliability.




Description

The BBT3420 is a quad 8-bit/10-bit parallel-to-serial and serial-to-parallel transceiver device ideal for high-bandwidth interconnection between line cards, serial backplanes, or optical modules, over interconnect media such as Printed Circuit Board (PCB) FR-4 traces or copper cables.

Each independent transceiver channel in BBT3420 is capable of operating at 2.488-3.1875Gbps at full-rate, and 1.244-1.59375Gbps at half-rate. The four on-chip transceivers shown in Figure 1-2 can also be configured as a single 10 Gigabit Attachment Unit Interface (XAUI), for both 10G Ethernet and 10G Fiber Channel or proprietary backplane interfaces, providing up to 12.75Gbps of data throughput at full duplex. The BBT3420 also supports the 10 Gigabit Media Independent Interface (XGMII) on the parallel interfaces. The device can be used as an XGMII Extended Sublayer (XGXS) device to support longer PCB traces between optical transceiver modules and switch fabrics, as shown in Figure 1-1.

As shown in Figure 1-3, each transceiver channel in BBT3420 contains a serializer, a deserializer, an 8b/10b encoder and decoder, as well as elastic buffers that provide the interface for serial data transmission and data recovery. Both the receive equalization and the transmit pre-emphasis are provided on each of the channels to maximize performance. In addition, a programmable receive FIFO in each channel aligns all incoming serial data to the local clock domain, adding or removing IDLE sequences as needed.

This in return will eliminate the need for multiple clock domains for the interfaced ASIC device to the transceiver. Each transceiver channel can also be configured to operate as a non-encoded 10-bit transceiver, allowing long strings of consecutive 1's or 0's (up to 512 bits). This feature enables the BBT3420 to accommodate proprietary encoded data links.

On each channel, the transmitter accepts up to 10-bit wide parallel SSTL_2 or HSTL Class I/O (Figure 2-1) data, which is then serialized into high-speed NRZ (Non-Return to Zero) serial streams. The effective serial output impedance is nominally 150 differential.

The BBT3420 transceiver can be configured via pins and through the Management Data Input/Output (MDIO) interface specified in IEEE 802.3 Clause 22 or Clause 45. The device supports both the 5-bit PHY address for Clause 22 and the 5-bit port address for Clause 45. The four device addresses for Clause 45 are user selectable. The device also supports the Built-in Self Test (BIST) and IEEE 1149.1 (JTAG) for self-test purposes including serial and parallel loopback under either external pin or MDIO control, and Pseudo Random Bit Sequence (PRBS) generation and verification.

The BBT3420 is assembled in a 289-pin 19mm x 19mm HSBGA package. The device can operate with a single 1.8V supply and dissipates only 250mW per channel.

In normal operation, the BBT3420 transmitters accept data from the parallel data bus, clocked by the appropriate Transmit Byte Clock for the channel, and resynchronize it into the Transmit FIFO using the local reference clock. The data is then optionally encoded using the standard 8B/10B encoder, serialized, and sent out on the differential CML, XAUI-compatible transmit pins. The BBT3420 receivers accept serial data from the CML receive pins, perform clock and data recovery on the bit stream, scan the data for the Comma patterns, Byte-Aligns the data on either disparity of the sync pattern, and de-serializes the data. The data is then optionally 8B/10B decoded and fed into the receiver FIFO, where clock compensation, optional channel alignment, and resynchronization to any one of the individual recovered clocks, one channel clock, or the local reference clock are performed. In addition, several other features are provided to ease system testing. Loopback at either the serial or parallel ports is available under external pin or MDIO control. Suitable control and status registers are available through the IEEE standard MDIO/MDC system. The XGMII interface can be configured in source-centered or source synchronous timing formats for ASIC-friendly timing. If the Built-in-Self-Test function (BIST) is in use, the serial transmit data is instead driven from a PRBS 223 -1 pattern generator. In the BIST mode, the received serial data is checked against the PRBS pattern transmitted and, if an error is found, a flag signal is provided.