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Am49PDL127AH

Features: Power dissipation- Operating: 40 mA maximum- Standby: 70 µA maximum- Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data retention supply voltage: 2.7 to 3.3 volt Byte data control: LB#s (DQ7DQ0), UB#s (DQ15DQ8) 8-word pag...

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SeekIC No. : 004283658 Detail

Am49PDL127AH: Features: Power dissipation- Operating: 40 mA maximum- Standby: 70 µA maximum- Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data r...

Am49PDL127AH Data Sheet

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Part Number:
Am49PDL127AH
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Power dissipation
- Operating: 40 mA maximum
- Standby: 70 µA maximum
- Deep power-down standby: 5 µA
CE1s# and CE2ps Chip Select
Power down features using CE1s# and CE2ps
Data retention supply voltage: 2.7 to 3.3 volt
Byte data control: LB#s (DQ7DQ0), UB#s (DQ15DQ8)
8-word page mode access


Specifications

Storage Temperature
Plastic Packages . . . . . . . . . . . 55°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . .  . 40°C to +85°C
Voltage with Respect to Ground
VCCf, VCCs (Note 1) . . . . . . . . . . .0.5 V to +4.0 V
RESET# (Note 2) . . . . . . . . . .. . .0.5 V to +12.5 V
WP#/ACC . . . . . . . . . . . . . . . . . .0.5 V to +10.5 V
All other pins (Note 1) . . . . .. 0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . 200 mA



Description

The Am49PDL127AH is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

Am49PDL127AH offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit memory space.




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