Am28F010

Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65 to +125
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .55 to + 125
Voltage with Respect To Ground
All pins except A9 and VPP (Note 1) .2.0 V to +7.0 V
V_CC (Note 1). . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V
V_PP (Note 2). . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V
Output Short Circuit Current (Note 3) . . . . . .  200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, inputs may overshoot V_SS to 2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is V_CC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to V_CC + 2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9 and VPP pins is -0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to 2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 and V_PP is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

The Am28F010 is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memory. The Am28F010 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers.The Am28F010 is erased when shipped from the factory.

The standard Am28F010 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F010 has separate chip enable (CE#) and output enable (OE#) controls

AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F010 uses a command register to manage this functionality, while maintaining a JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility.

AMD's Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F010 uses a 12.0V±5% V_PP high voltage input to perform the Flasherase and Flashrite algorithms.

The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from 1 V to V_CC +1 V.The Am28F010 is byte programmable using 10 ms programming pulses in accordance with AMD's Flashrite programming algorithm. The typical room temperature programming time of the Am28F010 is two seconds.The entire chip is bulk erased using 10 ms erase pulses according to AMD's Flasherase alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 1520 minutes required for EPROM erasure using ultra-violet light are eliminated.

Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry.During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification,the Am28F010 is designed to support either WE#or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.

AMD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F010 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.