AZ100LVEL33

The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state. RESET allows for the synchronization of multiple LVEL33's in a system.

The LVEL33 provides a VBB output for single-end use or a DC bias reference for AC coupling to the device.

For single-ended input applications, the VBB reference should be connected to one side of the CLK/ C¯¯L¯K¯  ifferential input pair. The input signal is then fed to the other CLK/ C¯¯L¯K¯ input. The VBB pin can support 1.0mA sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.