AZ100E111

The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q¯ outputs HIGH.

The AZ100E111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For singleended input applications, the VBB reference should be connected to one side of the IN/I¯N¯ differential input pair. The input signal is then fed to the other IN/IN ¯¯ input. The VBB pin should be used only as a bias for the E111 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01F capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, low skew device.

To ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50, even if only one side is used. In most applications all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.

NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.