AT76C506

• IEEE 802.11b MAC and Baseband for Supporting Standard Rates Up to 11 Mbps
• Wireless Interface Following the IEEE 802.11b Standard
• Wireless LAN MAC Unit with ARM7TDMI® RISC Processor
• Integrated 128-byte Transmit and 128-byte Receive FIFOs for Wireless MAC Layer Functions
• PCI Bus Interface Compliant with PCI v2.2 and PCI Power Management Specification v1.1
• Glueless SRAM Interface for All MAC Operations, Supporting up to 1M byte of External Memory
• Integrated 6K x 32-bit Internal SRAM, Used for Fast Program Code Execution and Temporary Storage of Data
• Glueless Flash Memory Interface, Supporting Up to 1M byte of Nonvolatile Memory for Permanent Storage of Program Code
• Wired Equivalency Privacy (WEP) in Hardware Supporting 64-bit and 128-bit Encryption
• The Integrated MAC Support Unit (MSU) Supports Timing Critical MAC Functions
• The WLAN and Inter-networking Functions can be Changed and Updated Easily to New Requirements Since They are Implemented in Microcode
• Supports 11 Mbps Rates with Automatic Fallback to 5.5, 2 and 1 Mbps
• 160-pin BGA Package
• Low-voltage 3.3V Operation
• SPI Interface and 2 GPIO Pins
• AT76C506 Offers the Option to Download the Whole Code from SPI DataFlash® or an Option to Eliminate Flash by the Program From the Mass Storage Device
• Integrated 802.11 Baseband Processor
• Baseband Supports Antenna Diversity Algorithm
• Baseband Supports Japan Filter
• Baseband Supports Differential or Single-ended I- and Q-Baseband Signals

The AT76C506 is a single-chip baseband controller that can handle IEEE 802.11b stan-dard compliant data rates of up to 11 Mbps and provides all processing and functionality needed for the MAC protocol of IEEE 802.11b. The AT76C506 is a slave PCI device that allows Host access to any memory location of the device including the on-chip reg- isters. Power management support conforming to PCI Power Management Specification v1.1 is also provided so that the device can be used for mini PCI applications.

Besides the PCI interface unit, the AT76C506 contains a WEP engine block, a MAC Support Unit (MSU), a 802.11b Baseband controller, a memory controller and the ARM® subsystem consisting of an Interrupt Controller, two 32-bit timers and an address decoder unit.

The AT76C506 core supports two alternative instruction sets. Powerful 32-bit code can be executed by the processor in ARM operating mode. However, a 16-bit instruction subset is also available in Thumb® mode. Thumb mode can be selected to exploit full processor power with limited external memory resources. Note that ARM7TDMI operat-ing mode can be changed at run time with negligible overhead.