AT76C504

• IEEE 802.11b Baseband and MAC for Supporting Standard Rates up to 11 Mbps
• Wireless Interface Following the IEEE 802.11b Standard
• Wireless LAN MAC Unit with ARM7TDMI® RISC Processor
• Integrated 128-byte Transmit and 128-byte Receive FIFOs for Wireless MAC Layer Functions
• 16-bit PCMCIA Bus Interface
• Glueless SRAM Interface for All MAC Operations, Supporting up to 1M Byte of External Memory
• Integrated 6K x 32-bit Internal SRAM, Used for Fast Program Code Execution and Temporary Storage of Data
• Glueless Flash Memory Interface, Supporting up to 1M Byte of Nonvolatile Memory for Permanent Storage of Program Code
• Wired Equivalency (WEP) in Hardware Supporting 64-bit and 128-bit Encryption
• The Integrated MAC Support Unit (MSU) Supports Timing Critical MAC Functions
• The WLAN and Inter-networking Functions Can be Changed and Updated Easily to New Requirements Since They are Implemented in Microcode
• Supports Automatic Fallback from 11 Mbps to 5.5, 2 and 1 Mbps
• 160-ball BGA Package
• Low-voltage 3.3V Operation
• Internal ROM Contains Hardwired CIS Information for Automatic Configuration when Card is Inserted in the PCMCIA Slot
• SPI Interface and 2 GPIO Pins
• AT76C504 Offers the Option to Download the Whole Code from SPI DataFlash® or an Option to Eliminate Flash by Downloading the Program from the Mass Storage Device
• Integrated 802.11b Baseband Processor
• Baseband Supports Antenna Diversity Algorithm
• Baseband Supports Differential or Single-ended I- and Q-Baseband Signals
• Baseband Supports Japan Filter

The AT76C504 is a single-chip baseband controller that can handle IEEE 802.11b stan-dard compliant data rates of up to 11 Mbps and provides all processing and functionality needed for the MAC protocol of IEEE 802.11b. AT76C 504 provides a glueless interface conforming to PC Card 95 and can support a variety of RF interfaces.

The AT76C504 chip incorporates an ARM7TDMI processor using a sophisticated archi-tecture to control the on-chip peripherals, manage the internal memory and allocate data queue buffers as well as to communicate with the host through the PCMCIA paral-lel bus. The processor peripheral logic consists of a PCMCIA bus interface, a Serial Peripheral Interface (SPI), a MAC unit, a 802.11b Baseband block, the common mem-ory interface, internal boot Read Only Memory (ROM) and the normal operation stages and common microcontroller blocks like timers, interrupt controller and bus arbiter.

The AT76C504 ARM7TDMI core supports two alternative instruction sets. Powerful 32-bit code can be executed by the processor in ARM® operating mode. However, a 16-bit instruction subset is also available in Thumb® mode. Thumb mode can be selected to exploit full processor power with limited external memory resources. Note that ARM7TDMI operat- ing mode can be changed at run time with negligible overhead.