AT28C16-T

· Ideal Rewriteable Attribute Memory
· Simple Write Operation Self-Timed Byte Writes On-chip Address and Data Latch for SRAM-like Write Operation Fast Write Cycle Time - 1 ms 5-Volt-Only Nonvolatile Writes
· End of Write Detection RDY/BUSY Output DATA Polling
· High Reliability Endurance: 100,000 Write Cycles Data Retention: 10 Years Minimum
· Single 5-Volt Supply for Read and Write
· Very Low Power 30 mA Active Current 100 mA Standby Current

Temperature Under Bias................... -55°C to +125°C
Storage Temperature....................... -65°C to +125°C

All Input Voltages(including NC Pins)
with Respect to Ground ....................... -0.6V to +6.25V

All Output Voltages
with Respect to Ground .................-0.6V to V_CC + 0.6V

Voltage on OE and A9
with Respect to Ground ...................... -0.6V to +13.5V

*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The AT28C16-T is the ideal nonvolatile attribute memory: it is a low power, 5-volt-only byte writeable nonvolatile memory (E²PROM). Standby current is typically less than 100 A. The AT28C16-T is written like a Static RAM, eliminating complex programming algorithms. The fast write cycle times of 1 ms, allow quick card reconfiguration in-system. Data retention is specified as 10 years minimum, precluding the necessity for batteries. Three access times have been specified to allow for varying layers of buffering between the memory and the PCMCIA interface.

The AT28C16-T is accessed like a Static RAM for read and write operations. During a byte write, the address and data are latched internally. Following the initiation of a write cycle, the device will go to a busy state and automatically write the latched data using an internal control timer. The device provides two methods for detecting the end of a write cycle; the RDY/BUSY output and DATA POLLING of I/O7.