Features: • Fast Read Access Time 120 ns• Automatic Page Write Operation -ternal Address and Data Latches for 128 Bytes -ternal Control Timer• Fast Write Cycle Time -ge Write Cycle Time 10 ms Maximum -to 128-byte Page Write Operation• Low Power Dissipation - mA Active Cur...
AT28C010-12DK: Features: • Fast Read Access Time 120 ns• Automatic Page Write Operation -ternal Address and Data Latches for 128 Bytes -ternal Control Timer• Fast Write Cycle Time -ge Write Cycl...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Temperature Under Bias.............................. -55°C to +125°C
Storage Temperature.................................. -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute aximum Ratings" may cause permanent damage o the device. This is a stress rating only and unctional operation of the device at these or any ther conditions beyond those indicated in the perational sections of this specification is not mplied. Exposure to absolute maximum rating onditions for extended periods may affect evice reliability.
The AT28C010-12DK is a high-performance Electrically Erasable and Programmable ead-Only Memory. Its one megabit of memory is organized as 131,072 words by 8 its. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device ffers access times to 120 ns with power dissipation of just 440 mW. When the device s deselected, the CMOS standby current is less than 300 A.
The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without he need for external components. The AT28C010-12DK contains a 128-byte page register to llow writing of up to 128 bytes simultaneously. During a write cycle, the address and to 128 bytes of data are internally latched, freeing the address and data bus for ther operations. Following the initiation of a write cycle, the device will automatically rite the latched data using an internal control timer. The end of a write cycle can be etected by DATA POLLING of I/O7. Once the end of a write cycle has been detected new access for a read or write can begin.
Atmel's AT28C010-12DKhas additional features to ensure high quality in manufacturing. The AT28C010-12DK utilizes internal error correction for extended endurance and improved data etention characteristics. An optional software data protection mechanism is available o guard against inadvertent writes. The AT28C010-12DK also includes an extra 128 bytes of EPROM for device identification or tracking.