AT17LV128

Features:

* EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
   2,097,152 x 1-, and 4,194,304 x 1-bit Serial
    Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
* Supports both 3.3V and 5.0V Operating Voltage Applications
* In-System Programmable (ISP) via Two-Wire Bus
* Simple Interface to SRAM FPGAs (R) (TM)
* Compatible with Atmel AT6000, AT40K and AT94K Devices,
    Altera FLEX , APEX (R) (TM) (TM) (TM) (R) (R) Devices, Lucent ORCA^® ,
     Xilinx XC3000 , XC4000 , XC5200 , Spartan , Virtex FPGAs
* Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
* Very Low-power CMOS EEPROM Process
* Programmable Reset Polarity
* Available in 6 mm x 6 mm x 1 mm 8-lead LAP
   (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP,
   8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP Packages
* Emulation of Atmel's AT24CXXX Serial EEPROMs
* Low-power Standby Mode
* High-reliability
Endurance: 100,000 Write Cycles
Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for Commercial Parts (at 70°C)

Pinout




Specifications

Operating Temperature.................................... -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground................ .................-0.1V to V_CC +0.5V
Supply Voltage (V_CC)............................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.)................260°C
ESD (R_ZAP= 1.5K, C_ZAP= 100 pF).........................................2000V
 


Description

The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The AT17LV series Configurators uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by pro-gramming four EEPROM bytes. These devices also support a write-protectionmechanism within its programming mode.

The AT17LV series configurators can be programmed with industry-standard program-mers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.