ASM5P2304B

*Zero input - output propagation delay, adjustable  by   capacitive load on FBK input. 
*Multiple configurations - Refer "ASM5P2304B  Configurations Table".  
* Input frequency range: 4MHz to 20MHz
* Multiple low-skew outputs.  
     *Output-output skew less than 200pS.  
    * Device-device skew less than 500pS.  
    *Two banks of four outputs.  
* Less than 200pS Cycle-to-Cycle jitter   (-1, -1H, -2, -2H).  
*Available in space saving, 8-pin 150 mil SOIC Package. 
*3.3V operation.  
*Advanced 0.35 CMOS technology.  
*Industrial temperature available. 
 

ASM5P2304B is a versatile, 3.3V zero-delay buffer  designed to distribute high-speed clocks in PC,  workstation, datacom, telecom and other high  performance  applications. It is available in an 8 pin package. The part has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to  be driven to FBK pin, and can be obtained from one of the  outputs. The input-to-output propagation delay of ASM5P2304B is guaranteed to be less than 250pS, and the output-to-output  skew is guaranteed to be less than 200pS. 

That has two banks of two outputs each.  Multiple ASM5P2304B devices can accept the same input  clock and distribute it. In this case the skew between the  outputs of the two devices is guaranteed to be less than  500pS. 

The ASM5P2304B is available in two different  configurations (Refer "ASM5P2304B Configurations Table).  It is the base part, where the output  frequencies equal the reference if there is no counter in the  feedback path. The ASM5P2304B-1H is the high-drive  version of the -1 and the rise and fall times on this device  are much faster. The ASM5P2304B-2 allows the user to  obtain REF and 1/2X or 2X frequencies on each output  bank. The exact configuration and output frequencies  depend on which output drives the feedback pin.