ASM5I961PG-32LR

The ASM5I961PG-32LR belongs to ASM5I961P family which is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay buffer and it is offered with two different input configurations offering an LVCMOS reference clock while the ASM5I961P offers an LVPECL reference clock. When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. With output frequencies of up to 200MHz, output skews of 150pS the device meets the needs of the most demanding clock tree applications. For series terminated lines the ASM5I961P can drive two lines per output giving the device an effective fanout of 1:36. ASM5I961PG-32LR is packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance. Because the OE pin does not affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock. the ASM5I961P is fully 2.5V or 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 transmission lines.

The features of ASM5I961PG-32LR can be summarized as (1)fully integrated PLL; (2)up to 200MHz I/O frequency; (3)LVCMOS outputs; (4)outputs disable in high impedance; (5)LVPECL reference clock options; (6)LQFP packaging; (7)±50pS cyclecycle jitter; (8)150pS output skews.

The absolute maximum ratings of ASM5I961PG-32LR are (1)VCC supply voltage: 0.3 to 3.6 V; (2)VIN DC input voltage: 0.3 to VCC + 0.3 V; (3)VOUT DC output voltage 0.3 to VCC + 0.3 V; (4)IIN DC input current: ±20 mA; (5)IOUT DC output current: ±50 mA; (6)TS storage temperature range: 40 to 125 °C; (7)TDV static discharge voltage (As per JEDEC STD 22- A114-B): 2 KV.