Features: ` AS6WA25616
` IntelliwattTMactive power circuitry
` Industrial and commercial temperature ranges available
` Organization: 262,144 words * 16 bits
`3.0V to 3.6V at 55 ns
`Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
`Low power consumption: STANDBY
- 72 W max at 3.6V
` 1.5V data retention
` Equal access and cycle times
` Easy memory expansion with CS, OE inputs
` Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
` ESD protection 2000 volts
` Latch-up current 200 mA
Pinout
Specifications
| Parameter |
Device |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to VSS |
|
VtIN |
-0.5 |
VCC+ 0.5 |
V |
| Voltage on any I/O pin relative to GND |
|
VtI/O |
0.5 |
|
V |
| Power dissipation |
|
PD |
|
1.0 |
W |
| Storage temperature (plastic) |
|
Tstg |
65 |
+150 |
|
Temperature with VCCapplied
|
|
Tbias |
55 |
+125 |
|
| DC output current (low) |
|
IOUT |
|
20 |
mA |
DescriptionThe AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words * 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access of AS6WA25616 and cycle times (tAA , t RC , tWC ) of 55ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 W power consumption at 3.6V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. and UB and/or LB low.Data on the input pins I/O1I/O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices of AS6WA25616 should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle of AS6WA25616 is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or (UB) and (LB),output drivers stay in high-impedance mode.
AS6WA25616 provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1I/O8, and UB controls the higher bits, I/O9I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply.AS6WA25616 is available in the JEDEC standard 400-mm, TSOP 2, and 48-ball FBGA packages.
AS6WA25616 Data Sheet
