Features: ` AS6UA5128
` IntelliwattTMactive power circuitry
` Industrial and commercial temperature ranges available
` Organization: 524,288 words * 8 bits
`2.7V to 3.6V at 55 ns
` 2.3V to 2.7V at 70 ns
`Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
`Low power consumption: STANDBY
- 72 W max at 3.6V
- 41 W max at 2.7V
- 28 W max at 2.3V
` 1.2V data retention
` Equal access and cycle times
` Easy memory expansion with CS, OE inputs
` Smallest footprint packages
- 36(48)-ball FBGA
- 32-pin TSOP I and TSOP II packages are available on Alliance AS6UB5128 product family (available January 2001)
` ESD protection 2000 volts
` Latch-up current 200 mASpecifications
| Parameter |
Device |
Symbol |
Min |
Max |
Unit |
| Voltage on VCC relative to VSS |
|
VtIN |
-0.5 |
VCC+ 0.5 |
V |
| Voltage on any I/O pin relative to GND |
|
VtI/O |
0.5 |
|
V |
| Power dissipation |
|
PD |
|
1.0 |
W |
| Storage temperature (plastic) |
|
Tstg |
65 |
+150 |
|
Temperature with VCCapplied
|
|
Tbias |
55 |
+125 |
|
| DC output current (low) |
|
IOUT |
|
20 |
mA |
DescriptionThe AS6UA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words * 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access of AS6UA5128 and cycle times (tAA , t RC , tWC ) of 55/70ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, the device enters standby mode: the AS6UA5128 is guaranteed not to exceed 72 W power consumption at 3.6V and 55 ns; 41 W at 2.7V and 70 ns; or 28 W at 2.3V and 100 ns. AS6UA5128 also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/O1I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle of AS6UA5128 is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.3V to 3.6V supply. AS6UA5128 is available in the JEDEC standard 36(48)-ball FBGA package.
AS6UA5128 Data Sheet
