AS4LC4M16S0

Features: • PC100/133 compliant• Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16)• Fully synchronous - All signals referenced to positive edge of clock• Four internal banks controlled by BA0/BA1 (bank select)• High...

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AS4LC4M16S0 Picture
SeekIC No. : 004288372 Detail

AS4LC4M16S0: Features: • PC100/133 compliant• Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16)• Fully synchronous - All signals referenced ...

floor Price/Ceiling Price

Part Number:
AS4LC4M16S0
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• PC100/133 compliant
• Organization
   - 2,097,152 words × 8 bits × 4 banks (8M×8)
   - 1,048,576 words × 16 bits × 4 banks (4M×16)
• Fully synchronous
   - All signals referenced to positive edge of clock
• Four internal banks controlled by BA0/BA1 (bank select)
• High speed
   - 133/125/100 MHz
   - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
• Low power consumption
   - Standby: 7.2 mW max, CMOS I/O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• Automatic and direct precharge
• Burst read, single write operation
• Can assert random column address in every cycle
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
   - 400 mil, 54-pin TSOP II
• Read/write data masking
• Programmable burst length (1/2/4/8/full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (2/3)



Pinout

  Connection Diagram


Specifications

Parameter
Symbol
Min
Max
Unit
Input voltage
VIN,VOUT
1.0
+4.6
V
Power supply voltage
VCC,VCCQ
1.0
+4.6
V
Storage temperature (plastic)
TSTG
55
+150
°C
Power dissipation
PD
1
W
Short circuit output current
IOUT
50
mA



Description

The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a new column address.

The four internal banks of AS4LC4M16S0 can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. This provides a significant advantage over asynchronous EDO and fast page mode devices.

This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature of AS4LC4M16S0 enables flexible performance optimization for a variety of applications.

DRAM commands and functions of AS4LC4M16S0 are decoded from control inputs. Basic commands are as follows:
• Mode register set                       • Deactivate bank              • Deactivate all banks                • Select row; activate bank
• Select column; write                   • Select column; read         • Deselect; power down            • CBR refresh
• Auto precharge with read/write • Self-refresh

The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL-compatible.




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