AK6003A

Features: ADVANCED CMOS EEPROM TECHNOLOGYREAD/WRITE NON-VOLATILE MEMORYWIDE VCC OPERATION  Vcc = 1.8V  5.5V2048 bits, 2568 organizationI2CTM SERIAL INTERFACELOW POWER CONSUMPTION - 0.8A Max. StandbyHIGH RELIABILITY - Endurance : 100K cycles - Data Retention : 10 years16 byte page write modeSof...

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SeekIC No. : 004279421 Detail

AK6003A: Features: ADVANCED CMOS EEPROM TECHNOLOGYREAD/WRITE NON-VOLATILE MEMORYWIDE VCC OPERATION  Vcc = 1.8V  5.5V2048 bits, 2568 organizationI2CTM SERIAL INTERFACELOW POWER CONSUMPTION - 0.8A Max. Sta...

floor Price/Ceiling Price

Part Number:
AK6003A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/24

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Product Details

Description



Features:

ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION  Vcc = 1.8V  5.5V
2048 bits, 2568 organization
I2CTM SERIAL INTERFACE
LOW POWER CONSUMPTION
   - 0.8A Max. Standby
HIGH RELIABILITY
   - Endurance : 100K cycles
   - Data Retention : 10 years
16 byte page write mode
Software Write Protection (lower 128 bytes)
  H
ardware Write Protection (entire array)
Automatic write cycle time-out with auto-ERASE
IDEAL FOR LOW DENSITY DATA STORAGE
   - Low cost, space saving, 8-pin package (TSSOP)




Pinout

  Connection Diagram


Specifications

  Connection Diagram


Description

The AK6003A is a 2048-bit serial CMOS E2PROM divided into 256 registers of 8 bits each.
The AK6003A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation.
The AK6003A conforms to all specifications in the 2 wire protocol and is controlled by serial clock (SK) and serial data (SDA) line.
Some devices can be connected to the same bus. Each AK6003A connected to the bus is software addressable by a unique address, and can operate as either a transmitter or receiver. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table1). The master is the device which initiates a data transfers on the bus and generates the clock signals to permit that transfer. At that time, the device addressed is considered as the slave.




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