ADSP-BF561

Features:

*Dual Symmetric 600 Mhz High Performance Blackfin Core
*328 KBytes of On-chip Memory (See Memory Info onPage3)
*Each Blackfin Core Includes:
     Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter
*RISC-Like Register and Instruction Model for Ease of Programming and Compiler-Friendly Support
*Advanced Debug, Trace, and Performance- Monitoring
*0.8 - 1.2V core V_DD with On-Chip Voltage Regulation
*3.3V and 2.5V Tolerant I/O
*256-Ball Mini BGA and 297-Ball PBGA Package Options


Specifications

Internal (Core) Supply Voltage¹  (V_DDINT)           0.3 V to +1.4 V
External (I/O) Supply Voltage¹  (V_DDEXT)             0.3 V to +3.8 V
Input Voltage¹                                                     0.5 V to 3.6 V
Output Voltage Swing¹                                        0.5 V to V_DDEXT+0.5 V
Load Capacitance^1,2                                            200 pF
Core Clock (CCLK)¹   
    ADSP-BF561SKBCZ600                                     600 MHz
    ADSP-BF561SKBCZ500                                     500 MHz
System Clock (SCLK)¹                                          133 MHz
Storage Temperature Range¹                             65 to +150
Junction Temperature Under Bias                        125
Lead Temperature (5 seconds)¹                          185oC


¹.Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


².For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3V) or 30 pF (at 2.5V) for ADDR25-2, DATA31-0, ABE3-0/SDQM3-0, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.

Description

The ADSP-BF561 processor is a high-performance member of the Blackfin family of products targeting a variety of multimedia and elecommunications applications. At the heart of this device are two independent Analog Devices Blackfin processors. These Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantage of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The ADSP-BF561 device integrates a general purpose set of digital imaging peripherals creating a complete system on-chip solution for digital imaging and multimedia applications.


The ADSP-BF561 processor has 328 KBytes of on-chip mem-ory. Each Blackfin core includes:
* 16K Bytes of Instruction SRAM/Cache
* 16K Bytes of Instruction SRAM
* 32K Bytes of Data SRAM/Cache
* 32K Bytes of Data SRAM
* 4K Bytes of Scratchpad SRAM


Additional on-chip memory peripherals of ADSP-BF561 include:
* 128 KBytes of Low Latency On-chip SRAM
* Four Channel Internal Memory DMA Controller
* External Memory controller with glueless support for SDRAM, SRAM, and Flash.