Features: ADSP-219x, 16-Bit, Fixed Point DSP Core with up to 160 MIPS Sustained Performance
40K Words of On-Chip RAM, Configured as 32K Words On-Chip 24-Bit Program RAM and 8K Words On-Chip 16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation Circuitry Enables Full Speed Operation from Low Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System, with up to 20 MSPS Sampling Rate (at 160 MHz Core Clock Rate)
Three Phase 16-Bit Center Based PWM Generation Unit with 12.5 ns Resolution at 160 MHz Core Clock (CCLK) Rate
Dedicated 32-Bit Encoder Interface Unit with Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave Operation
Synchronous Serial Communications Port (SPORT) Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software Priority Control
Multiple Boot Modes
Precision 1.0 V Voltage ReferenceApplicationIndustrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable InstrumentationSpecificationsInternal (Core) Supply Voltage1 (VDDINT) . . 0.3 V to +3.0 V
External (I/O) Supply Voltage1 (VDDEXT). . . 0.3 V to +4.6 V
Input Voltage1, 2 (VILVIH) . . . . . . . . . . . . . 0.5 V to +5.5 V
Output Voltage Swing1, 2 (VOLVOH) . . . . . . 0.5 V to +5.5 V
Load Capacitance1 (CL). . . . . . . . . . . . . . . . . . . . . . 200 pF
Core Clock Period1 (tCCLK). . . . . . . . . . . . . . . . . . . . 6.25 ns
Core Clock Frequency1 (fCCLK) . . . . . . . . . . . . . . 160 MHz
Peripheral Clock Period1 (tHCLK) . . . . . . . . . . . . . . . 12.5 ns
Peripheral Clock Frequency1 (fHCLK) . . . . . . . . . . . 80 MHz
Storage Temperature Range1 (TSTORE) . . . .65ºC to +150ºC
Lead Temperature (5 seconds)1 (TLEAD) . . . . . . . . . . . 185ºCDescriptionThe ADSP-21991 is a mixed signal DSP controller based on the ADSP-219x DSP Core, suitable for a variety of high performance industrial motor control and signal processing applications that require the combination of a high performance DSP and the mixed signal integration of embedded control peripherals such as analog-to-digital conversion.
The ADSP-21991 integrates the fixed point ADSP-219x family base architecture with a serial port, an SPI compatible port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.
The architecture is code compatible with previous ADSP-217x based ADMCxxx products. Although the architectures are compatible, the ADSP-21991, with ADSP-219x architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data address generators, and program sequencer make the ADSP-21991 more flexible and easier to program than the previous ADSP-21xx embedded DSPs.
Indirect addressing options provide addressing flexibility- premodify with no update, pre- and post-modify by an immediate 8-bit, twos complement value and base address registers for easier implementation of circular buffering.
The ADSP-21991 integrates 40K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 8K words (16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the ADSP-21991 operates with a 6.25 ns instruction cycle time for a 160 MHz CCLK and with a 6.67 ns instruction cycle time for a 150 MHz CCLK. All instructions, except two multiword instructions, execute in a single DSP cycle.
ADSP-21991 Data Sheet
