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ADSP-2186

Features: PERFORMANCE25 ns Instruction Cycle Time 40 MIPS SustainedPerformanceSingle-Cycle Instruction ExecutionSingle-Cycle Context Switch3-Bus Architecture Allows Dual Operand Fetches inEvery Instruction CycleMultifunction InstructionsPower-Down Mode Featuring Low CMOS StandbyPower Dissipation w...

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SeekIC No. : 004277586 Detail

ADSP-2186: Features: PERFORMANCE25 ns Instruction Cycle Time 40 MIPS SustainedPerformanceSingle-Cycle Instruction ExecutionSingle-Cycle Context Switch3-Bus Architecture Allows Dual Operand Fetches inEvery Inst...

ADSP-2186 Data Sheet

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Part Number:
ADSP-2186
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Memory RAM and
8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
144-Ball Mini-BGA
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits "Glueless" System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems


Pinout

Connection Diagram


Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . .. . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . .. . 0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . 40 to +85
Storage Temperature Range . . . . . . . . . . . 65 to +150
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280


Description

The ADSP-2186 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2186 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities and on-chip program and data memory.

The ADSP-2186 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment.

The ADSP-2186 is available in 100-lead LQFP and 144-Ball Mini-BGA packages.

In addition, the ADSP-2186 supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test-new ALU constants, new multiplication instruction (x squared),biased rounding, result free ALU operations, I/O memory transICE-fers and global interrupt masking for increased flexibility.




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