ADSP-21368

At 400 MHz (2.5 ns) core instruction rate, the ADSP-21368 performs 2.4 GFLOPS/800 MMACS
2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and 250K bit in blocks 2 and 3) for simultaneous access by the core processor and DMA
6M bit on-chip, mask-programmable, ROM (3M bit in block 0 and 3M bit in block 1)
Dual data address generators (DAGs) with modulo and bitreverse addressing
Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture provides:
     Two computational processing elements
     Concurrent execution
     Code compatibility with other SHARC family members at the assembly level
     Parallelism in buses and computational units allows: single cycle executions (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch
Transfers between memory and core at a sustained 6.4G bytes/s bandwidth at 400 MHz core instruction rate

The ADSP-21368 SHARC processor is a members of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21368 is source code compatible with the ADSP-2126x, and ADSP-2116x, DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single- Instruction, Single-Data) mode. The product is a 32- bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip SRAM, and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

As shown in the functional block diagram on Page 1, the product uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21368 processor achieves an instruction cycle time of 2.5 ns at 400 MHz. With its SIMD computational hardware, the ADSP-21368 can perform 2.4 GFLOPS running at 400 MHz.