Features: `DMA controller
`Six full duplex serial ports
` Two SPI-compatible interface ports-primary on dedi-cated pins, secondary on DAI pins
`Digital Audio Interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converters, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) buses
Specifications
| Parameter |
Rating |
Internal (Core) Supply Voltage (VDDINT)1
Analog (PLL) Supply Voltage (AVDD)1
External (I/O) Supply Voltage (VDDEXT)1
Input Voltage0.5 V to VDDEXT 1
Output Voltage Swing0.5 V to VDDEXT 1
Load Capacitance 1
Storage Temperature Range
Junction Temperature under Bias
|
0.3 V to +1.5 V
0.3 V to +1.5 V
0.3 V to +4.6 V
+ 0.5 V
+ 0.5 V
200 pF
65 C to +150
125 |
1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DescriptionThe ADSP-21365/6 SHARC processors are members of the SIMD SHARC family of DSPs that feature Analog Devices'
Super Harvard Architecture. The ADSP-21365/6 are source code compatible with the ADSP-2126x, and ADSP-2116x, DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. The products are 32-bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).
As shown in the functional block diagram onpage1, the ADSP-21365/6 uses two computational units to deliver a signif-icant performance increase over the previous SHARC processors on a range of signal processing algorithms. Fabri-cated in a state-of-the-art, high speed, CMOS process, the ADSP-21365/6 processor achieves an instruction cycle time of 3.0 ns at 333 MHz. With its SIMD computational hardware, the ADSP-21365/6 can perform 2 GFLOPS running at 333 MHz.
Table1 shows performance benchmarks for the ADSP-21365/6.
ADSP-21366 Data Sheet
