Features: ` DMA controller
` Six full duplex serial ports
` Two SPI-compatible interface ports-primary on dedi- cated pins secondary on DAI pins
` Digital Audio Interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample rate converters, six serial ports, eight serial interfaces, a 20- bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU)
Specifications
| Parameter |
Rating |
Internal (Core) Supply Voltage (VDDINT)1
Analog (PLL) Supply Voltage (AVDD)1
External (I/O) Supply Voltage (VDDEXT)1
Input Voltage0.5 V to VDDEXT 1
Output Voltage Swing0.5 V to VDDEXT 1
Load Capacitance 1
Storage Temperature Range
Junction Temperature under Bias
|
0.3 V to +1.5 V
0.3 V to +1.5 V
0.3 V to +4.6 V
+ 0.5 V
+ 0.5 V
200 pF
65 C to +150
125 |
1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DescriptionThe ADSP-21364 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Har- vard Architecture. The ADSP-21364 is source code compatible with the ADSP-2126x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Sin- gle-Instruction, Single-Data) mode. The product is a 32- bit/40-bit floating point processor optimized for professional audio applications with a large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).
As shown in the functional block diagram onPage1, the ADSP-21364 uses two computational units to deliver a signifi- cant performance increase over previous SHARC processors on a range of signal processing algorithms. Fabricated in a state-of- the-art, high speed, CMOS process, the product processor achieves an instruction cycle time of 3.0 ns at 333 MHz.
With its SIMD computational hardware, the ADSP-21364 can perform 2 GFLOPS running at 333 MHz. Table1 shows performance benchmarks for the ADSP-21364.
ADSP-21364 Data Sheet
