ADSP-21362

At 333 MHz (3.0 ns) core instruction rate, the ADSP-21362 performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA
Dual data address generators (DAGs) with modulo and bitreverse addressing
Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing
 Single-Instruction Multiple-Data (SIMD) architecture provides:
    Two computational processing elements
    Concurrent execution
    Code compatibility with other SHARC family members at the assembly level
    Parallelism in buses and computational units allows single cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch
Transfers between memory and core at a sustained 5.4G bytes/s bandwidth at 333 MHz core instruction rate INPUT/OUTPUT FEATURES

The ADSP-21362 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21362 are source codecompatible with the ADSP-2126x, and ADSP-2116x, DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. The product are 32-bit/40-bit floating-point processors optimized for high performance automotive audio applications with their large onchip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI).

As shown in the functional block diagram on Page 1,it uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. Fabricated in a stateof- the-art, high speed, CMOS process, the ADSP-21362 processor achieve an instruction cycle time of 3.0 ns at 333 MHz. With its SIMD computational hardware, the ADSP-21362 can perform 2 GFLOPS running at 333 MHz.