ADSP-21267

• Two processing elements, each containing an ALU, Multiplier, Shifter and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle
• Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulse width Measurement, and External Event Counter Capabilities
• On-Chip dual-ported SRAM (1 Mbit)
• On-Chip dual-ported, mask-programmable ROM (3 Mbits)
• JTAG test access port
• 8- or 16-bit Parallel port that supports interfaces to off-chip memory peripherals
• DMA controller
• Four full-duplex serial ports
• SPI-compatible interface
• Digital Audio Interface that includes two precision clock generators (PCG), an input data port (IDP), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)

Internal (Core) Supply Voltage (VDDINT)¹ ...........0.3 V to +1.5 V
Analog (PLL) Supply Voltage (AVDD)¹ .................-0.3 V to +1.5 V
External (I/O) Supply Voltage (VDDEXT)¹ ...........-0.3 V to +4.6 V
Input Voltage ....................................-0.5 V to VDDEXT ¹ + 0.5 V
Output Voltage Swing .......................-0.5 V to VDDEXT ¹ + 0.5 V
Load Capacitance¹ ...........................................................200 pF
Storage Temperature Range1 ..........................-65°C to +150°C

1)Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Harvard Architecture. The ADSP-21267 is source code compatible with the ADSP-21236x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single- Instruction, Single-Data) mode. Like other SHARC DSPs, the product is a 32-bit/40-bit floating-point processor optimized for high performance audio applications with its dualported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

As shown in the Functional Block Diagram on page 1, it uses two computational units to deliver a significant performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21267 DSP achieves an instruction cycle time of 6.6 ns at 150 MHz. With its SIMD computational hardware, the ADSP-21267 can perform 900 MFLOPS running at 150 MHz.