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ADSP-21160M

Features: ` 80 MHz (12.5 ns) Core Instruction Rate` Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units` 480 MFLOPS Peak and 320 MFLOPS Sustained Performance (Based on FIR)` Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing` Zero-Overh...

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SeekIC No. : 004277443 Detail

ADSP-21160M: Features: ` 80 MHz (12.5 ns) Core Instruction Rate` Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units` 480 MFLOPS Peak and 320 MFLOPS Sustained Performance (B...

ADSP-21160M Data Sheet

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Part Number:
ADSP-21160M
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
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Product Details

Description



Features:

` 80 MHz (12.5 ns) Core Instruction Rate
` Single-Cycle Instruction Execution, Including SIMD
  Operations in Both Computational Units
` 480 MFLOPS Peak and 320 MFLOPS Sustained
  Performance (Based on FIR)
` Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing
` Zero-Overhead Looping and Single-Cycle Loop Setup,Providing Efficient Program Sequencing
` IEEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation
` 400-Ball 27*27 mm Metric PBGA Package
` Single Instruction Multiple Data (SIMD)
  Architecture Provides:
  Two Computational Processing Elements
  Concurrent Execution-Each Processing Element
  Executes the Same Instruction, but Operates on Different Data
  Code Compatibility-at Assembly Level, Uses the
  Same Instruction Set as the ADSP-2106x SHARC DSPs
` Parallelism in Buses and Computational Units Allows:
  Single-cycle Execution (with or without SIMD) of: A
  Multiply Operation, An ALU Operation, A Dual Memory Read or Write, and An Instruction Fetch
  Transfers Between Memory and Core at up to Four 32-Bit Floating- or Fixed-Point Words per Cycle
  Accelerated FFT Butterfly Computation Through a Multiply with Add and Subtract
` 4M Bit On-Chip Dual-Ported SRAM for Independent
  Access by Core Processor, Host, and DMA
` DMA Controller supports:
  14 Zero-Overhead DMA Channels for Transfers Between
  ADSP-21160M Internal Memory and External
  Memory, External Peripherals, Host Processor, Serial Ports, or Link Ports
  64-Bit Background DMA Transfers at Core Clock Speed, in Parallel with Full-Speed Processor Execution
  560M Bytes/s Transfer Rate Over IOP Bus
  Host Processor Interface to 16- and 32-Bit Microprocessors
` 4G Word Address Range for Off-Chip Memory
` Memory Interface Supports Programmable Wait State
  Generation and Page-Mode for Off-Chip Memory
` Multiprocessing Support Provides:
  Glueless Connection for Scalable DSP Multiprocessing Architecture
  Distributed On-Chip Bus Arbitration for Parallel Bus
  Connect of up to Six ADSP-21160Ms plus Host
  Six Link Ports for Point-To-Point Connectivity and Array Multiprocessing
` Serial Ports Provide:
  Two 40M Bit/s Synchronous Serial Ports with
  Companding Hardware
  Independent Transmit and Receive Functions
  TDM Support for T1 and E1 Interfaces
` 64-Bit Wide Synchronous External Port Provides:
  Glueless Connection to Asynchronous and SBSRAM External Memories
  Up to 40 MHz Operation


Specifications

Internal (Core) Supply Voltage (VDDINT)1 . . .0.3 V to +3.0 V
Analog (PLL) Supply Voltage (AVDD) . . . . .....0.3 V to +3.0 V
External (I/O) Supply Voltage (VDDEXT) . . . ..0.3 V to +4.6 V
Input Voltage. . . . . . . . . . . . . . . . . ...0.5 V to VDDEXT+0.5 V
Output Voltage Swing . . . . . . . . . . ...0.5 V to VDDEXT+0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . .... . . . 200 pF
Storage Temperature Range . . . . . . . . . .  65ºC to +150ºC
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . .. 185ºC

1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


Description

The ADSP-21160M SHARC DSP is the first processor in a new family featuring Analog Devices' Super Harvard Architecture. Easing portability, it is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor's SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, it is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160M includes an 80 MHz core, a dual-ported on-chip SRAM, anintegrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.

The ADSP-21160M introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), it can double performance versus the ADSP-2106x on a range of DSP algorithms.

Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21160M has a 12.5 ns instruction cycle time. With its SIMD computational hardware running at 80 MHz, the ADSP-21160M can perform 480 million math operations per second.




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