Features: 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution120 MFLOPS Peak, 80 MFLOPS Sustained PerformanceDual Data Address Generators with Modulo and Bit- Reverse AddressingEfficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop SetupIEEE JTAG Standard 1149.1...
ADSP-21060LC: Features: 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution120 MFLOPS Peak, 80 MFLOPS Sustained PerformanceDual Data Address Generators with Modulo and Bit- Reverse AddressingEffic...
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The ADSP-2106x SHARC-Super Harvard Architecture Computer -is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP- 21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.