ADSP-21060LC

Features: 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution120 MFLOPS Peak, 80 MFLOPS Sustained PerformanceDual Data Address Generators with Modulo and Bit- Reverse AddressingEfficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop SetupIEEE JTAG Standard 1149.1...

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SeekIC No. : 004277417 Detail

ADSP-21060LC: Features: 40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution120 MFLOPS Peak, 80 MFLOPS Sustained PerformanceDual Data Address Generators with Modulo and Bit- Reverse AddressingEffic...

floor Price/Ceiling Price

Part Number:
ADSP-21060LC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/12

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Product Details

Description



Features:

40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit- Reverse Addressing
Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation
240-Lead Thermally Enhanced CQFP Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed- Point Data Format



Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . .0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . .65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . 280°C



Description

The ADSP-2106x SHARC-Super Harvard Architecture Computer -is a signal processing microcomputer that offers new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP- 21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-2106x.

The ADSP-2106x SHARC represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.




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