ADF4007

Features:

7.5 GHz bandwidth
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allowsextended tuning voltage in 3 V systems
R_SET contol of charge pump current
Hardware power-down mode




Application

Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs





Pinout








Specifications

AV_DD to GND¹ −0.3 V to +3.6 V
AV_DD to DVDD −0.3 V to +0.3 V
V_P to GND −0.3 V to +5.8 V
V_P to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to V_DD + 0.3 V
Analog I/O Voltage to GND −0.3 V to V_P + 0.3 V
REF_IN, RFI_NA, RFI_NB to GND−0.3 V to V_DD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range−65°C to +125°C
Maximum Junction Temperature 150°C
CSP _JA Thermal Impedance 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
Transistor Count
CMOS 6425
Bipolar303






Description

The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. ADF4007 consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider/prescaler. The divider/ prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REFIN frequency of up to 240 MHz.

A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). ADF4007's very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.