Features: 155 Mbps Clock Recovery and Data RetimingPermits CCITT G.958 Type A Jitter TolerancePermits CCITT G.958 Type B Jitter TransferRandom Jitter: 0.68 rmsPattern Jitter: Virtually EliminatedSpecificationsSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VInput...
AD805*: Features: 155 Mbps Clock Recovery and Data RetimingPermits CCITT G.958 Type A Jitter TolerancePermits CCITT G.958 Type B Jitter TransferRandom Jitter: 0.68 rmsPattern Jitter: Virtually EliminatedSpe...
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The AD805-VCXO circuit meets or exceeds CCITT G.958 regenerator specifications for STM-I Type A jitter tolerance and STM-1 Type B jitter transfer. The simultaneous Type A, wideband jitter tolerance and Type B, narrow-band jitter transfer allows the use of the AD805-VCXO circuit in a regenerative application to overcome optical line system interworking limitations based on signal retiming using Type A passive tuned device technology such as Surface Acoustic-Wave (SAW) or dielectric resonator filters, with Type B active devices such as Phase-Locked Loops (PLLs).
The circuit VCXO provides a stable and accurate clock frequency signal with or without input data. The AD805 works with the VCXO to dynamically adjust the recovered clock frequency to the frequency associated with the input data. This frequency control loop tracks any low frequency component of jitter on the input data. Since the circuit uses the VCXO for clock recovery, it has a high Q for excellent wideband jitter attenuation. The jitter transfer characteristic of the circuit is within the jitter transfer requirements for a CCITT G.958 STM-1 Type B regenerator, which has a corner frequency of 30 kHz.
Output jitter, determined primarily by the VCXO, is a very low 0.6° rms. Jitter due to variations in input data density, pattern jitter, is virtually eliminated in the circuit due to the AD805's patented phase detector. The data retiming loop of the AD805 can be used with a passive tuned circuit (155.52 MHz) such as a bandpass or a SAW filter for clock recovery and data retiming. The data retiming loop acts to servo the phase of the input data to the phase of the recovered clock from the passive tuned circuit in this type of application (see APPLICATIONS).